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Department of Electrical and Computer Engineering, University of Kuwait, P.O. Box 5969, Safat 13060, Kuwait

ABSTRACT

In this paper the effect of permanent and intermittent faults on sequential circuits is analyzed. An off-line testing procedure for intermittent and permanent faults is proposed. This procedure is analyzed mathematically by deriving an expression for the distribution function of the error latency of an intermittent fault as a function of n input vectors. Sequential circuits are divided into input and output circuits. A graph model is used to analyze input and output circuit faults. The testing procedure for both types is described and a testing model is presented. Simulation is used to produce the mean value of the length of the input sequence needed to detect a given fault. The results of the mathematical manipulation and simulation are compared.