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*Department of Electrical and Computer Engineering, Concordia University, Canada E-mail:s.ebrahim.e@gmail.com

** Department of Electrical Engineering, Kuwait University, Kuwait.

E-mail: nabil. khachab@ku.edu.kw

ABSTRACT

The increased flexibility offered by FPGAs implies that more transistors are needed which leads to higher power consumption per logic gate. FPGAs power consumption is fast becoming an essential design consideration, especially for mobile systems with a limited power supply. The effect of components region-constrained placement on reducing internal nets total capacitance and the corresponding change in internal nets total dynamic power consumption is investigated. Combinational and sequential logic circuits were specified as components covering around 80% of total FPGA busy gates. Each of these components was implemented on two of Xilinx FPGAs families, namely: Spartan II and Virtex. Gate-level power estimation for different region-constrained placements of each logic circuit was carried out using the Xilinx hierarchal power distribution analyzer, XPower. The correlation coefficient between the change in the capacitance and the corresponding change in power consumption was calculated for nine logic circuits. Simulation results show that although substantial reduction in internal nets capacitance is achievable through region-constrained placements of components, the expected gain of reduced dynamic power consumption is dependent on the logic circuit being implemented. In the case of arithmetic circuits where glitches are common, there has been an observable negative relationship between internal nets capacitance reduction and the anticipated reduction in the dynamic power. The objective of placement should not be restricted to reducing the interconnect capacitance C, but it should be expanded to include the reduction of the effective capacitance \alpha C.

Keywords: Dynamic power; FPGAs; glitches; power consumption; placement.