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Volume :14 Issue : 2 1987      Add To Cart                                                                    Download

Reconfigurable architecture using cascadable bit-slice emulators

Auther : JAVIN M. TAYLOR AND MANSOUR H. JARAGH

Department of Electrical and Computer Engineering, New Mexico State University, Las Cruces, N.M., U.S.A., and Department of Electrical and Computer Engineering, University of Kuwait, P.O. Box: 5969, Safat, 13060, Kuwait

 

 

ABSTRACT

 

This paper describes a reconfigurable emulation system designed with the objective of having the ability to emulate most of the common microprocessors. The system is rnicroprogrammable, flexible and cascadable. It can emulate 8, 16 and 32 bit microprocessors. Furthermore, the system can enhance the performance of an existing microprocessor by modifying its hardware and extending its software.

            Bit-slice technology is used in the design. Each emulator module consists of a CPU and a sequencer module. The basic CPU function performs eight-bit operations and contains 32 eight bit registers. The sequencer function uses 108-bit microinstructions and has 1 K by 108-bit control store which contains the emulation microcode.

 

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